What is RISC-V?

Sep 30, 2021

CPUs run a set of low-level instructions that perform fundamental operations for all programs – loading values, storing values, arithmetic, and interfacing with memory.

The set of all such instructions is called an instruction set architecture (ISA). Each vendor (e.g. Intel or ARM) has their own proprietary ISA – x86 for Intel or ARM for, well, ARM. ARM differs from x86 by implementation, but also because it belongs to a subset of architectures called "Reduced Instruction Set Computer" (RISC), which is pretty much what it sounds like. This makes it much easier to build against. That's why they teach RISC architectures like MIPS in school (I learned MIPS and they still teach it!). RISC architectures have usually been used for embedded use cases (phones, IoT devices).

But what is RISC-V?

RISC-V ("risk-five") is an open standard instruction set architecture based on RISC principles.

Unlike other architectures, RISC-V is completely open source and free to use.

The authors outline their rationale in a paper called Instruction Sets Should Be Free: The Case For RISC-V

Not only is RISC-V good for reducing vendor lock-in (to AMD or Intel), but it's also (relatively) easy to implement and extend. It won't replace AMD or x86 right away, but I imagine more and more devices will target RISC-V in the future, and that should open the door to even more innovation.

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